1. Field of the Invention
The present invention relates to forming electrical contacts in a semiconductor substrate. More particularly, the present invention relates to forming electrical conductors through the entire thickness of a semiconductor substrate for electrically coupling opposing sides of the substrate.
2. State of the Art
Integrated circuit devices are typically manufactured as individual circuits which are repeatedly formed in a pattern across the surface of a semiconductor substrate. Because of processing variations and contaminations across the surface of a semiconductor substrate, various ones of the individual integrated circuits will necessarily not function or perform as designed. Rather than identifying the defective ones of the integrated circuits at a much later stage during or after the packaging of individual integrated circuit devices, it is desirable to identify and reject defective devices at as early of a stage as possible and prior to further costly and time-consuming processing and testing.
Wafer-level testing of integrated circuits on a semiconductor substrate is one conventional approach for identifying defective integrated circuits at an early testing stage. Wafer-level testing involves coupling electrical testing probes to an integrated circuit when it is still integral with other ones of integrated circuits on the semiconductor substrate. Because of the fine-pitch or small dimensions associated with the contact or bond pads of each of the integrated circuits, the fabrication and mechanical coupling of the electrically conductive test probes has been both expensive and unreliable. One conventional wafer-level testing approach has been to employ a probe card which includes fine-pitched probes which correspond to the series of integrated circuits located across the semiconductor substrate, which substrate may also be commonly referred to as a “wafer-under-test.” The formation of such probe cards is both time consuming and expensive, since each contact probe must be accurately located on the probe card and individually physically populated. Additionally, each integrated circuit contact or bond pad arrangement fabricated on a semiconductor substrate is unique and, under the conventional probe card approach, would require the development of a correspondingly unique probe card for that design.
Accordingly, there has been a need to form a fine-pitched electrically conductive coupling mechanism for coupling with the fine-pitched contact or bond pads of integrated circuits located across a semiconductor substrate. Formation of an intermediary coupling mechanism such as a contactor card for locating between a semiconductor substrate (e.g., a wafer-under-test) and a probe card of a testing system has been attempted. The contactor card by necessity needs to electrically couple signals from its first side to its second or opposing side. While the electrical signals can be routed on either side to a nondirectly opposing arrangement, the signals must be necessarily routed from one side or face through the entire contactor card to a second or opposing face. One conventional approach for electrically coupling a signal from a first side of a wafer-scale contactor card to a second side involved the formation of a physical hole entirely through the thickness dimension of the contactor card. To facilitate electrical conduction through the physical hole, conductive (solder) paste was screened into the hole. Because of the imprecise application process and inconsistency of the conductive paste through the hole, gases and solvents easily become trapped and isolated within the conductive paste-based contact.
While electrical continuity through a gas- or solvent-trapped conductive paste contact is generally adequate at room temperature, wafer-level testing undergoes temperature cycling to further stress marginally functional integrated circuits on the semiconductor substrate. Accordingly, the contactor card also undergoes temperature cycling alongside the wafer-under-test; however, the mismatch of coefficients of thermal expansion (CTE) of the solder paste and silicon of the wafer-scale contactor card as well as the presence of trapped gases and solvents frequently causes a conductive paste-based contact to fracture, which may result in unreliable conductivity with the contact or bond pad of the wafer-under-test. Therefore, there exists a need to form a reliable contact through a wafer-scale semiconductor substrate contactor card that provides an electrically reliable connection and withstands temperature cycling during testing.